1. Field of the Invention
The present invention relates to a semiconductor device, or more in particular to a semiconductor device in which a plurality of semiconductor elements of various types are formed in electrically insulated relations with each other on an insulating layer.
2. Description of the Related Art
The power MOS transistor which is a kind of semiconductor has various features. First, it has a high input impedance and a large current gain. Secondly, it is capable of high-speed operation. Thirdly, its operation is stable against thermal effect. For these features, the transistor is expected to find wide applications to a large-power switching device or the like. The vertical double-diffused MOS transistor (hereinafter referred to as "DMOS"), which is a kind of power MOS transistor, has a superior breakdown voltage and high-frequency characteristic as semiconductor elements. A perspective sectional view of a conventional structure of such a DMOS is shown in FIG. 6.
In the conventional structure shown in FIG. 6, an N.sup.+ -type silicon single-crystal substrate connected to a drain 100 and an N.sup.- type epitaxial layer 102 lower in impurities concentration than the silicon single-crystal substrate 101 and laid on the top of the silicon single-crystal substrate 101, make up a drain region. A P-type well region 103 is formed in the N.sup.- type epitaxial layer 102. Further, the P-type well region 103 has formed therein an N.sup.+ -type source region 104 electrically connected to a source 107. In the next, a gate electrode layer 105 is formed in an interlayer insulating film 106 formed to cover both the N.sup.+ -type source region 104 and the N.sup.- type epitaxial layer 102, and after that, the source 107 is so formed that the DMOS should be configured as a result.
In FIG. 6, a hatched arrow indicates the direction of currents that flow in the case where the drain 100 is impressed with a positive potential, the N.sup.+ -type source 104 and the P-type well region 103 are grounded, and the gate electrode layer 105 is supplied with the required potential.
The above-described conventional DMOS structure is such that the drain 100 is connected to the whole reverse surface of the silicon single-crystal substrate 101, and is shared by all the semiconductor elements on the substrate 101. As a result, it is impossible to configure a DMOS of N-type channel and a DMOS of P-type channel on the same semiconductor substrate.
On the other hand, a complementary circuit or the like which has the functions of horizontal MOS transistors of both P-type and N-type channels such as CMOS has been conventionally suggested. In such a circuit, electrical isolation between semiconductor elements is effected by a PN junction, so that it is always necessary to reversely bias the semiconductor substrate or the well region against the PN junction. Also, the elements are liable to be broken by a latch-up. Another problem is that if the device is operated at about the PN junction breakdown temperature Tj (=150.degree. C.), the leak current increases, thereby reducing the reliability.